1. Field of the Invention
The present invention relates to a sense amplifier used for a semiconductor integrated circuit such as an SRAM (Static Random Memory).
2. Related Background Art
FIG. 18 is a circuit of the conventional sense amplifier. The sense amplifier of FIG. 18 has PMOS transistors Q1 and Q2 composing a current mirror circuit, a pair of NMOS transistors Q3 and Q4 connected to the current mirror circuit, and an NMOS transistor Q5 connected between source terminals of the NMOS transistors Q3 and Q4, and a ground terminal. The gate terminals of the NMOS transistors Q3 and Q4 are connected to a pair of bit lines BL and /BL, and a sense signal is outputted via an inverter IV10 from a connection point between the PMOS transistor Q2 and the NMOS transistor Q4.
Because it is desirable that electrical properties of a pair of the NMOS transistors Q3 and Q4 are equal, channel widths, channel lengths and threshold voltages of the NMOS transistors Q3 and Q4 are equalized to each other.
However, due to dispersion in fabrication, sizes and threshold voltages of the NMOS transistors Q3 and Q4 are not necessarily equal to each other. Because of this, when the voltage difference of the pair of bit lines is small, due to the dispersion of the threshold voltages of the NMOS transistors Q3 and Q4, the output of the sense amplifier becomes a polarity opposite to the original polarity according to circumstances. The minimum voltage difference between the pair of the bit lines necessary for normalizing the output of the sense amplifier is called as an input offset voltage, merely an offset voltage or an offset.
Hereinafter, the problem of the conventional technologies will be explained based on an example of the sense amplifier used for the SRAM.
The sense amplifier used for the SRAM amplifies a very little voltage difference between the pair of bit lines for transferring data of the memory cell. Because the voltage difference between the pair of bit lines is generated due to the current drawn the memory cell, the longer the time required for the memory cell to draw the current from the bit lines is, the larger the voltage difference becomes. When the voltage difference surpasses the offset voltage of the memory cell, the sense operation is carried out for the first time. Accordingly, if it is necessary to operate the SRAM at a high speed, it is desirable to speed up the sense operation by minifying the offset voltage of the sense amplifier.
Here, it is assumed that the sense timing of the sense amplifier is adjusted by using a dummy bit line sense amplifier for sensing a dummy bit line. In this case, it is desirable to decide the timing that the dummy bit line sense amplifier outputs an output signal, based on only the voltage difference of the dummy bit line without depending on an activation signal from outside.
FIG. 19 is a conventional dummy bit line sense amplifier, an output of which varies in accordance with the input voltage difference. The sense circuit 2 performs the sense operation based on the output of the dummy bit line sense amplifier 1. If the offset voltage of the dummy bit line sense amplifier is different from each chip, the activation timing of the sense amplifier fluctuates. Because of this, it is desirable to set the offset voltage to be, for example 0V.
There is a single-phase input sense amplifier as shown in FIG. 20 as the dummy bit line sense amplifier. In this case, the timing in which the sense output is obtained is decided by the threshold voltage Vth of the transistor Q7 in the dummy bit line sense amplifier. Because the threshold voltage Vth fluctuates in the chip, for example, if the threshold voltage Vth of the transistor Q7 becomes small, the output timing of the dummy bit line sense amplifier becomes early, thereby causing a malfunction.
Incidentally, the gate length of the transistor composing the sense amplifier and the dummy bit line sense amplifier fluctuates wafer by wafer or lot by lot due to fabrication dispersion. It is well known that as the gate length is shorter, the threshold voltage Vth of the transistor fluctuates largely. When the gate length becomes short, the offset voltage of the sense amplifier or the dummy bit line sense amplifier becomes large. Because of this, there is a likelihood that a malfunction occurs if the activation signal of the sense amplifier is not delayed.